DK-DEV-5SGXEA7N【PDF 184/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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6-28

Receiver Clocking for Stratix V Devices

SV51007

2014.01.10

Receiver Clocking for Stratix V Devices

The fractional PLL receives the external clock input and generates different phases of the same clock. The

DPA block automatically chooses one of the clocks from the fractional PLL and aligns the incoming data

on each channel.

The synchronizer circuit is a 1 bit wide by 6 bit deep FIFO buffer that compensates for any phase difference

between the DPA clock and the data realignment block. If necessary, the user-controlled data realignment

circuitry inserts a single bit of latency in the serial bit stream to align to the word boundary. The deserializer

includes shift registers and parallel load registers, and sends a maximum of 10 bits to the internal logic.

The physical medium connecting the transmitter and receiver LVDS channels may introduce skew between

the serial data and the source-synchronous clock. The instantaneous skew between each LVDS channel and

the clock also varies with the jitter on the data and clock signals as seen by the receiver. The three different

modes — non-DPA, DPA, and soft-CDR — provide different options to overcome skew between the source

synchronous clock (non-DPA, DPA) /reference clock (soft-CDR) and the serial data.

Non-DPA mode allows you to statically select the optimal phase between the source synchronous clock and

the received serial data to compensate skew. In DPA mode, the DPA circuitry automatically chooses the

best phase to compensate for the skew between the source synchronous clock and the received serial data.

Soft-CDR mode provides opportunities for synchronous and asynchronous applications for chip-to-chip

and short reach board-to-board applications for SGMII protocols.

Note: Only the non-DPA mode requires manual skew adjustment.

Related Information

Guideline: Use PLLs in Integer PLL Mode for LVDS on page 6-8

Differential I/O Termination for Stratix V Devices

The Stratix V devices provide a 100 Ω , on-chip differential termination option on each differential receiver

channel for LVDS standards. On-chip termination saves board space by eliminating the need to add external

resistors on the board. You can enable on-chip termination in the Quartus II software Assignment Editor.

All I/O pins and dedicated clock input pins support on-chip differential termination, R D OCT.

Figure 6-27: On-Chip Differential I/O Termination

Differential Receiver

LVDS

Transmitter

with On-Chip 100 Ω

Termination

Z 0 = 50 Ω

R D

Z 0 = 50 Ω

Table 6-12: Quartus II Software Assignment Editor — On-Chip Differential Termination

This table lists the assignment name for on-chip differential termination in the Quartus II software Assignment

Editor.

To

Altera Corporation

Field

Assignment

rx_in

High-Speed Differential I/O Interfaces and DPA in Stratix V Devices

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